1. Field of the Invention
This invention relates to integrated circuit structures. More particularly, this invention relates to an improvement in the formation of self-aligned metal silicide contacts for MOS devices in integrated circuit structures, wherein a single step is used to form metal silicide over both the gate electrode and the source/drain regions.
2. Description of the Related Art
In the formation of MOS devices on integrated circuit structures, metal silicide portions are conventionally formed over the polysilicon gate electrode and over the source/drain regions of the silicon substrate to reduce the contact resistance, as well as to provide low interconnect and gate delay. This is illustrated in prior art FIG. 1, wherein a silicon substrate 2 is shown with source/drain regions 4, 6, and 8 formed therein and metal silicide portions 10, 12, and 14 formed respectively thereover. Between source/drain regions 4 and 6 (and metal silicide portions 10 and 12 thereon) is a polysilicon gate electrode 16 formed over a gate oxide 18 on substrate 2. Sidewall insulation spacers 20 and 22 (e.g., oxide spacers) are formed on the sidewalls of gate electrode 16 to respectively insulate gate electrode 16 from source/drain region 4 and metal silicide portion 10 thereon, and source/drain region 6 and metal silicon portion 12 thereon. A polysilicon gate electrode 24 for a second MOS transistor is similarly formed between source/drain regions 6 and 8 over a gate oxide 26 on substrate 2. Sidewall insulation spacers 28 and 30 are formed on the sidewalls of gate electrode 24 to respectively insulate gate electrode 24 from source/drain region 6 and metal silicide portion 12 thereon, and source/drain region 8 and metal silicon portion 14 thereon. Metal silicide portions 32 and 34 are shown respectively formed over the top surfaces of polysilicon gate electrodes 16 and 24.
In the structure shown in FIG. 1, metal silicide portions 10, 12, 14, 32, and 34 may be formed at the same time by a blanket deposition of a silicide-forming metal over source/drain regions 4, 6, and 8, sidewall spacers 20, 22, 28, and 30, as well as over polysilicon gate electrodes 16 and 24. Annealing such a structure results in a reaction between the silicide-forming metal and silicon surfaces in contact with the metal to form the desired metal silicide portions respectively over source/drain regions 4, 6, and 8, and over polysilicon gate electrodes 16 and 24. The silicide-forming metal over the insulation spacers does not react and this metal may then be selectively removed, using an etch system selective to the metal silicide and the sidewall insulation spacers.
While the foregoing prior art structure provides a simple way of forming self-aligned metal silicide (salicide) over the source/drain regions and gate electrode in a single silicide-forming step, it is sometimes difficult to subsequently form a properly aligned contact opening to the metal silicide over a source/drain region between two closely spaced apart gate electrodes, as shown in FIG. 1. This problem is exacerbated as contact areas shrink with ever smaller and smaller devices and closer spacing of devices on the semiconductor substrate. As illustrated in FIG. 1, a misaligned contact opening 36 is inadvertently formed in a dielectric layer 38 over the MOS structure, so that both metal silicide 12 over source/drain region 6 and metal silicide 32 over gate electrode 16 are exposed. Subsequent filling of misaligned contact opening 36 with metal 40 will result in an electrical short between source/drain region 6 and gate electrode 16.
To remedy this problem in the prior art, a self-aligned contact opening construction was developed wherein the metal silicide over the gate electrode was formed in a separate process step and then covered with an insulation material prior to formation of the source/drain metal silicide. Subsequent formation of a misaligned contact opening to the source/drain region did not result in exposure to the metal silicide over the gate electrode as long as the dielectric material over the metal silicide on the gate electrode was different from the material used in forming the overlying dielectric layer in which the source/drain contact opening was formed.
Formation of such a structure is shown in FIGS. 2A-2F. In FIG. 2A, a gate oxide layer 50 is first formed over silicon substrate 2 followed by blanket deposition of polysilicon layer 52. A metal silicide layer 54 is then formed over polysilicon layer 52 and a first insulation layer 56, e.g., silicon nitride, is formed over metal silicide layer 54. The polysilicon, metal silicide, and first insulation layers are then patterned to form a polysilicon gate electrode 52a having a metal silicide portion 54a thereon with gate insulation 56a formed over metal silicide portion 54a, as shown in FIG. 2B. Source/drain regions 4 and 6 may then be formed in substrate 2 followed by deposition of a conformal layer of a second insulation layer 58, which may comprise the same material as first insulation layer 56, as shown in FIG. 2C. Sidewall insulation spacers 60 and 62 are then formed from second insulation layer 58 by anisotropic etching of layer 58, as shown in FIG. 2D, which also results in removal of the unexposed portions of gate oxide layer 50, leaving gate oxide 50a beneath polysilicon gate electrode 52a. Self-aligned metal silicide source/drain portions 64 and 66 are then respectively formed over source/drain regions 4 and 6, as shown in FIG. 2E. A third insulation layer 68 is then formed over the structure comprising a different material from first and second insulation layers 56 and 58 materials from which gate insulation 56a and insulation spacers 60 and 62 were formed. When a misaligned contact opening 70 is then formed to metal silicide 66 over source/drain region 6 through third insulation layer 68, as shown in FIG. 2F, gate insulation material 56a over metal silicide gate portion 54a prevents gate metal silicide gate portion 54a from exposure. Subsequently filling of misaligned source/drain contact opening 70 with metal 72 to form a contact to metal silicide source/drain portion 64 does not result in undesirable electrical contact to metal silicide gate portion 54a and the MOS device is not shorted out.
While the construction just described, and illustrated in FIGS. 2A-2F, does remedy the problem of electrical shorting between the gate and one of the source/drain regions resulting from misaligned contact openings, it results in a need to provide two steps for the respective formation of metal silicide over the gate electrodes, and metal silicide over the source/drain regions, resulting in the need for further annealing steps (sometimes two annealing steps are required for each metal silicide formation, depending upon the metal used for the silicide formation), which has a negative impact on the overall thermal budget (total amount of heat exposure) for the construction of the integrated circuit structure.
It would, therefore, be desirable to provide a process wherein the gate electrode of an MOS device would be protected from inadvertent shorting to an adjacent source/drain region without, however, requiring multiple steps for the respective formations of metal silicide over the gate electrode and metal silicide over the source/drain regions.